module  sdram_write(
        input                   clk             ,
        input                   wr              ,

        input       [15:0]      data            ,
        input                   refresh_flag    ,
        input       [24:0]      addr            ,
        
        output      [15:0]      dq              ,
        output      [1:0]       dqm             ,
        output      [12:0]      write_addr      ,
        output      [1:0]       write_ba        ,
        output      [ 2:0]      cmd             ,
        output  reg             write_end_flag
);

/////////////////////命令 ras_n cas_n we_n

parameter               [2:0]           CMD_PRECHARGE 		=       3'b010;
parameter               [2:0]           CMD_WRITE     		=       3'b100;
parameter               [2:0]           CMD_NOP       		=       3'b111;

////////////////////状态
reg[4:0] current_state ;
parameter
//空闲
idle_state                                      =       5'b00110,
//写
write_state=5'b11100,
NOP_write_state1=5'b11101,
NOP_write_state2=5'b11110,
//预充电
Precharge_state                                 =       5'b01100,
Precharge_NOP_state                             =       5'b01101;


///////////////////主程序

always @(posedge clk)//状态机
    begin
		
		case (current_state)
            idle_state:
                begin
                    if(wr && !refresh_flag)
                        current_state=write_state;
                    else
                        current_state=idle_state;
                end
            write_state:
                begin
                    write_end_flag=1'b0;
                    current_state=NOP_write_state1;
                end
                NOP_write_state1:
                    begin
                        current_state=NOP_write_state2;
                    end
                NOP_write_state2:
                    begin					  
                            if(wr && !refresh_flag)
                            begin
                                current_state=write_state;
                            end
                        else
                            begin
                                current_state=Precharge_state;
                            end 
                    end
            Precharge_state:
                begin
                    current_state=Precharge_NOP_state;
                end
                Precharge_NOP_state:// tRP 15ns
                    begin
                        write_end_flag=1'b1;
                        current_state=idle_state;
                    end
            default : current_state<=idle_state;
        endcase
    end		

//数据
assign dq=(current_state==write_state)?data:{16{1'bz}};

//命令
assign cmd =(current_state==write_state)?CMD_WRITE:
            (current_state==Precharge_state)?CMD_PRECHARGE:CMD_NOP;

//地址 
assign {write_ba,write_addr}=(current_state==write_state)?{addr[24:23],3'b000,addr[9:0]}:
                              (current_state==Precharge_state)? {15{1'b1}}:{15{1'b0}};
//数据掩码
assign dqm = (current_state==write_state)?2'b00:2'b11;

endmodule